1. Technical Field
The present invention relates to an engineering change order (ECO) cell and a method for arranging and routing the same.
2. Description of the Related Art
A standard cell type LSI design engineering is widely used as a layout design engineering for implementing a large scale integrated circuit (LSI) having high integration on a semiconductor substrate for a short period of time. In the standard cell type LSI design engineering, a small unit circuit, such as an inverter and a NAND gate, is prepared as the standard cell, and the standard cell is arranged in array form and is connected to each other to form the LSI.
Hereinafter, an ECO cell in accordance with the related art will be described in more detail with reference to the accompanying drawings.
FIG. 1 shows a layout of a standard cell type LSI in accordance with the related art, and FIG. 2 shows an inner pattern view of a standard cell in accordance with the related art.
As shown in FIG. 1, a plurality of cell arrays are arranged, and each of cell arrays is formed by a plurality of standard cell 1006 having the same width (in other words, depth in drawings) and is arranged in array form.
A routing channel 1801 is arranged between the neighboring standard cell arrays. An inner-cell connection unit 1802 for connection between standard cells is included in the same standard cell array and an inter-array connection unit 1803 for connection between standard cells is included in different standard cell arrays which are located on routing channel 1801.
An ECO cell is provided in a design based on the standard cell library
The ECO cell in accordance with the related art will be described in more detail with reference to FIG. 2.
As shown in FIG. 2, ECO cell 200 includes a VDD power layer 202 for a VDD power supply, an N-diffusion layer 205 for a pick-up and a first contact hole 204, which connects VDD power layer 202 with N-diffusion layer 205, in an N-well 201.
A lower side of ECO cell 200 includes a VSS power layer 211 for a VSS power supply, a P-diffusion layer 210 for a pick-up and a second contact hole 209, which connects VSS power layer 211 with P-diffusion layer 210, and has an N-diffusion layer 208 and a poly gate 206 for making an NMOS included in various circuits.
Here, the NMOS poly gate and the PMOS poly gate are formed to be a single body.
However, the ECO cell in accordance with the related art has a problem as described below.
As described above, in the case that the cell library is used in the ECO cell, since a size of the cell library is predetermined, the flexibility is limited in a place step of the standard cell. Moreover, since a junction capacitance of the transistor is increased, the performance of the cell library used in the ECO cell will not be good.
In detail, since the ECO cell library having a fixed width is adapted in a cell library layout and a grid based auto place and root (P&R) tool is adapted, the flexibility of a cell layout is lowered.
Moreover, a connection between the PMOS of the ECO cell and the gate electrode of the NMOS is limited to generate various logic functions.
Accordingly, it is limited to respond to a request of a designer.